The memories are becoming a major part of any Application Specific Integrated Chip (“ASIC”) today. In fact, it is predicted that in coming years the memories will occupy ninety percent (90%) of the total chip area. Therefore, the performance of any ASIC will mostly be dependent upon performance of memories. Since memories cannot test themselves, they are tested either using Built In Self Test (BIST) or any other external circuitry. Redundancy is provided in the memories in the form of extra rows or columns so that the memories can be repaired if they are faulty.
In the present scenario, fuses are implemented on a chip with small/medium size memories, and the same number of fuses is allocated as the number of redundant bits required for all memories. The BIST runs to first calculate the faulty locations and makes a decision whether the faults can be repaired depending upon the available redundancy in the memory or on the chip. In case the memory is not repairable, the BIST declares the memory as dead. After the first BIST run on memory the following configurations can arise.
CONFIGURATIONSBBADREPAIRABLERepair StatusMemory is DEAD‘1’‘0’“0”Memory is GOOD‘0’‘0’“0”Memory is BAD but‘1’‘1’“1”repairableMemory is‘0’‘1’“0”repaired
Faulty Memory Repairable Bitmap (FMRB) consists of the faulty address (to be replaced by a available redundancy) and repair status. The repair status is ‘1’ when the memory is to be repaired and 0 if the memory is good. The calculated FMRB present in the BIST is shifted out to the fuse through a shift register. The FMRB shift register of all the BISTs are connected in big single chain, which is further connected to the fuse box as well as to the chip output port. The above shifted data is stored in the fuse and after the memory is repaired the BIST is run again to approve that.
But since only a very small number of the cuts are faulty on the same die, it is not an economical solution to have the fuse bits for all memories on chip, as it leads to an increase in area as a greater number of fuse macros are required on the chip. In order to overcome the above drawback, the concept of fuse sharing is used. In this methodology, the data is stored in the fuse with very few fuses actually present on the chip. The concept of fuse sharing has been shown in FIG. 1. The number of fuses used are “k” while “M” cuts with redundancy are present on the chip, which as total FMRB length of “N” bits. The “k” bit fuse data is converted into the data form the “M” cuts present on memory or N bits. In reality only “M” memories are failing with the total FMRB length less than “k” bits. The k bit fuse data can be divided into the following main parts:
1. Header: single bit data giving the repair status, the number “m”.
2. Address data (Kad): the address information relating to m faulty memories out of M memories.
3. Repair data (Krd): the repair data bit stream of “m” repairable and faulty memories.
But to store the data in k fuses the FMRB length of each memory should be known to the central controller, which will store the information in the “k” fuses. This information can be stored in the chip in a hard Read Only Memory (ROM), or a soft ROM. This information can also be sent along with the repair data, but then it will take more time to shift in the data. The die will be repairable if the value of k is greater than or equal to the summation of the value of header data, address data and repair data.
The advantages the above approach offers are reduced fuse area, reduced yield loss due to increased area, less time required for programming the fuse and reduced efforts at the user end. Yet it has a lot of drawbacks, as the problem of routing congestion is not addressed. Yield loss due to metal routing for M cuts is still present and the k to N converter requires a lot of area. An extra ROM is used which increases the overhead in terms of area and testing time.
To reduce routing congestion the fuse data can be serially shifted out as shown in the FIG. 2. The serial shifting improves the yield as a lot of parallel bus routing is reduced. Also yield loss due to parallel bus routing is reduced. But serial loading of fuse data for M cuts takes a lot of clock cycles at power on. The ROM utilized to store the repair data length increases overhead in terms of area and bits to be tested through dedicated BIST. Further extra area overhead in Test Manager Design (not yet included) is required with complex finite state machines (FSM) for encoding and decoding.
The present invention aims at solving problems created due to the above mentioned disadvantages. The ROM is completely eliminated in the present invention due to which extra overhead in terms of area is reduced as well as state machines for fuse encoding and decoding have become simpler. The repair data compression before storing it in the fuse had also been proposed so that more memories can be repaired with the same number of fuses in case die yield goes down.